The present invention generally relates to semiconductor memory devices, and more particularly, to a flash memory device and a method of manufacturing the same, in which an interference phenomenon can be reduced.
As the level of integration of NAND flash memories becomes high, the influence of cells adjacent to a programmed cell on the programmed cell is gradually increased.
Capacitance exists between cells that are adjacent to each other in a bit line direction (or x direction), a word line direction (or y direction), and a xy direction. The capacitance gradually increases as the distance between the cells becomes smaller as the level of integration of devices becomes higher. More particularly, the capacitance is significantly increased when the cells shrink in the x direction.
As a result, as the coupling ratio is reduced, the program speed is lowered and the interference phenomenon is increased.
The term “interference phenomenon” refers to a phenomenon in which if a neighboring cell to a to-be read cell is to be programmed, a threshold voltage of a cell, which is higher than an actual threshold voltage, is read due to the capacitance effect of an adjacently programmed cell during the read operation of a next cell because of variation in the charge of the floating gates of the neighboring cell. In this case, the charge itself of the floating gate of the to-be read cell is not changed, but the status of an actual cell looks distorted due to variation in the status of the neighboring cell.
This distortion phenomenon widens the distributions of cells and, therefore, makes it difficult to control the cells. More particularly, the influence is significantly greater in multi-level cells having a small cell distribution margin than in single-level cells.
To improve the cell uniformity, it is necessary to reduce the interference phenomenon.